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| Features * Industry-standard Architecture - Low-cost, Easy-to-use Software Tools * High-speed, Electrically Erasable Programmable Logic Devices - 5 ns Maximum Pin-to-pin Delay * Latch Feature Holds Inputs to Previous Logic States * Pin-controlled Standby Power (10 A Typical) * Advanced Flash Technology - Reprogrammable - 100% Tested High-reliability CMOS Process - 20-year Data Retention - 100 Erase/Write Cycles - 2,000V ESD Protection - 200 mA Latch-up Immunity Dual Inline and Surface Mount Packages in Standard Pinouts PCI-compliant Green Package Options (Pb/Halide-free/RoHS Compliant) Available Full Military, Commercial and Industrial Temperature Ranges Backward-Compatible with ATF22V10B(Q) and AT22V10(L) * Highperformance EE PLD ATF22V10C ATF22V10CQ See separate datasheet for the ATF22V10CQZ. * * * * * 1. Description The ATF22V10C is a high-performance CMOS (electrically erasable) programmable logic device (PLD) that utilizes Atmel's proven electrically erasable Flash memory technology. Speeds down to 5 ns and power dissipation as low as 100 A are offered. All speed ranges are specified over the full 5V 10% range for military and industrial temperature ranges, and 5V 5% for commercial temperature ranges. Several low-power options allow selection of the best solution for various types of power-limited applications. Each of these options significantly reduces total system power and enhances system reliability. 0735T-PLD-5/09 Figure 1-1. Logic Diagram 2. Pin Configurations Table 2-1. Pin Name CLK IN I/O GND VCC PD Pin Configurations (All Pinouts Top View) Function Clock Logic Inputs Bi-directional Buffers Ground +5V Supply Power-down Figure 2-1. CLK/IN IN IN IN/PD IN IN IN IN IN IN IN GND TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN Figure 2-2. DIP/SOIC CLK/IN IN IN IN/PD IN IN IN IN IN IN IN GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN Figure 2-3. PLCC/LCC IN IN CLK/IN VCC* VCC I/O I/O 4 3 2 1 28 27 26 Note: For all PLCCs (except "-5"), pins 1, 8, 15 and 22 can be left unconnected. However, if they are connected, superior performance will be achieved. 2 ATF22V10C(Q) 0735T-PLD-5/09 IN IN GND GND* IN I/O I/O 12 13 14 15 16 17 18 IN/PD IN IN GND* IN IN IN 5 6 7 8 9 10 11 25 24 23 22 21 20 19 I/O I/O I/O GND* I/O I/O I/O ATF22V10C(Q) 3. Absolute Maximum Ratings* Temperature under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.0V(1) Voltage on Input Pins with Respect to Ground during Programming .....................................-2.0V to +14.0V(1) Programming Voltage with Respect to Ground .......................................-2.0V to +14.0V(1) *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: 1. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC, which may overshoot to 7.0V for pulses of less than 20 ns. 4. DC and AC Operating Conditions Commercial Operating Temperature (Ambient) VCC Power Supply 0C - 70C 5V 5% Industrial -40C - 85C 5V 10% Military -55C - 125C (case) 5V 10% 3 0735T-PLD-5/09 4.1 DC Characteristics Parameter Input or I/O Low Leakage Current Input or I/O High Leakage Current Condition 0 VIN VIL (Max) 3.5 VIN VCC C-5, 7, 10 C-10 Com. Ind., Mil. Com. Ind., Mil. Com. Ind. Com. Ind., Mil. Com. Ind., Mil. Com. Ind. Com. Ind. 70.0 70.0 40.0 40.0 10.0 10.0 85.0 90.0 65.0 65.0 35.0 35.0 Min Typ Max -10.0 10.0 130.0 140.0 90.0 115.0 55.0 70.0 150.0 160.0 90.0 90.0 60.0 80.0 100.0 100.0 -130.0 -0.5 2.0 VIN = VIH or VIL, VCC = Min VIN = VIH or VIL, VCC = Min IOL = 16 mA IOL = 12 mA IOH = -4.0 mA Com., Ind. Mil. 2.4 0.8 VCC+0.75 0.5 0.5 Units A A mA mA mA mA mA mA mA mA mA mA mA mA A A mA V V V V V Symbol IIL IIH ICC Power Supply Current, Standby VCC = Max, VIN = Max, Outputs Open C-15 C-15 CQ-15 CQ-15 C-5, 7, 10 C-10 ICC2 Clocked Power Supply Current VCC = Max, Outputs Open, f = 15 MHz C-15 C-15 CQ-15 CQ-15 IPD IOS(1) VIL VIH VOL VOH Note: Power Supply Current, PD Mode Output Short Circuit Current Input Low Voltage Input High Voltage Output Low Voltage VCC = Max VIN = 0, Max VOUT = 0.5V Output High Voltage 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. 4 ATF22V10C(Q) 0735T-PLD-5/09 ATF22V10C(Q) 4.2 AC Waveforms (1) CLOCK Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified. 4.3 AC Characteristics(1) -5 -7 Max 5.0 4.0 2.5 3.0 0 142.0 166.0 166.0 3.0 2.0 2.0 3.0 5.5 4.0 4.0 4.0 6.0 5.0 7.0 3.5 0 125.0 (3) -10 Max 7.5 4.5(2) 2.5 4.5 0 90.0 117.0 125.0 3.0 7.5 7.5 10.0 3.0 3.0 3.0 8.0 6.0 6.0 8.0 10.0 9.0 12.0 Min 3.0 2.0 Max 10.0 6.5 2.5 10.0 0 55.5 80.0 83.3 6.0 3.0 3.0 3.0 Min 3.0 2.0 -15 Max 15.0 8.0 2.5 Units ns ns ns ns ns MHz MHz MHz ns 15.0 15.0 20.0 15.0 10.0 10.0 10.0 ns ns ns ns ns ns ns Symbol tPD tCO tCF tS tH Parameter Input or Feedback to Combinatorial Output Clock to Output Clock to Feedback Input or Feedback Setup Time Hold Time External Feedback 1/(tS + tCO) Min 1.0 1.0 Min 3.0 2.0 fMAX Internal Feedback 1/(tS + tCF) No Feedback 1/(tWH + tWL) 142.0 166.0 3.0 3.0 3.0 3.0 7.0 5.0 4.5 5.0 tW tEA tER tAP tAW tAR tSP tSPR Notes: Clock Width (tWL and tWH) Input or I/O to Output Enable Input or I/O to Output Disable Input or I/O to Asynchronous Reset of Register Asynchronous Reset Width Asynchronous Reset Recovery Time Setup Time, Synchronous Preset Synchronous Preset to Clock Recovery Time 2. 5.5 ns for DIP package devices. 3. 111 MHz for DIP package devices. 1. See ordering information for valid part numbers. 5 0735T-PLD-5/09 4.4 Power-down AC Characteristics(1)(2)(3) -5 -7 Max Min 7.5 0 0 5.0 5.0 5.0 5.0 15.0 15.0 20.0 7.0 7.0 7.0 7.5 20.0 20.0 25.0 Max Min 10.0 0 0 10.0 10.0 10.0 10.0 25.0 25.0 30.0 15.0 15.0 15.0 15.0 30.0 30.0 35.0 -10 Max Min 15.0 0 -15 Max Units ns ns ns ns ns ns ns ns ns ns Parameter Valid Input before PD High Valid OE before PD High Valid Clock before PD High Input Don't Care after PD High OE Don't Care after PD High Clock Don't Care after PD High PD Low to Valid Input PD Low to Valid OE PD Low to Valid Clock PD Low to Valid Output 1. Output data is latched and held. 2. High-Z outputs remain high-Z. 3. Clock and input transitions are ignored. Min 5.0 0 0 Symbol tIVDH tGVDH tCVDH tDHIX tDHGX tDHCX tDLIV tDLGV tDLCV tDLOV Notes: 4.5 4.5.1 Input Test Waveforms Input Test Waveforms and Measurement Levels 4.5.2 Commercial Output Test Loads 4.6 Pin Capacitance Table 4-1. Pin Capacitance (f = 1 MHz, T = 25C(1)) Typ CIN COUT Note: 5 6 Max 8 8 Units pF pF Conditions VIN = 0V VOUT = 0V 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. 6 ATF22V10C(Q) 0735T-PLD-5/09 ATF22V10C(Q) 4.7 Power-up Reset The registers in the ATF22V10Cs are designed to reset during power-up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic, and starts below 0.7V, 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and 3. The clock must remain stable during tPR. Figure 4-1. Power-up Reset Timing V RST POWER t PR REGISTERED OUTPUTS tW CLOCK tS 4.8 Preload of Registered Outputs The ATF22V10C's registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically by most of the approved programmers after the programming. 5. Electronic Signature Word There are 64 bits of programmable memory that are always available to the user, even if the device is secured. These bits can be used for user-specific data. 6. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF22V10C fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible. The security fuse should be programmed last, as its effect is immediate. 7 0735T-PLD-5/09 7. Programming/Erasing Programming/erasing is performed using standard PLD programmers. See "CMOS PLD Programming Hardware & Software Support" for information on software/programming. Table 7-1. Parameter tPR VRST Programming/Erasing Description Power-up Reset Time Power-up Reset Voltage Typ 600 3.8 Max 1,000 4.5 Units ns V 8. Input and I/O Pin-keeper Circuits The ATF22V10C contains internal input and I/O pin-keeper circuits. These circuits allow each ATF22V10C pin to hold its previous value even when it is not being driven by an external source or by the device's output buffer. This helps to ensure that all logic array inputs are at known valid logic levels. This reduces system power by preventing pins from floating to indeterminate levels. By using pin-keeper circuits rather than pull-up resistors, there is no DC current required to hold the pins in either logic state (high or low). These pin-keeper circuits are implemented as weak feedback inverters, as shown in the Input Diagram below. These keeper circuits can easily be overdriven by standard TTL- or CMOS-compatible drivers. The typical overdrive current required is 40 A. Figure 8-1. Input Diagram 8 ATF22V10C(Q) 0735T-PLD-5/09 ATF22V10C(Q) Figure 8-2. I/O Diagram 9. Power-down Mode The ATF22V10C includes an optional pin-controlled power-down feature. When this mode is enabled, the PD pin acts as the power-down pin (Pin 4 on the DIP/SOIC packages and Pin 5 on the PLCC package). When the PD pin is high, the device supply current is reduced to less than 100 mA. During power-down, all output data and internal logic states are latched and held. Therefore, all registered and combinatorial output data remain valid. Any outputs that were in an undetermined state at the onset of power-down will remain at the same state. During powerdown, all input signals except the power-down pin are blocked. Input and I/O hold latches remain active to ensure that pins do not float to indeterminate levels, further reducing system power. The power-down pin feature is enabled in the logic design file. Designs using the powerdown pin may not use the PD pin logic array input. However, all other PD pin macrocell resources may still be used, including the buried feedback and foldback product term array inputs. PD pin configuration is controlled by the design file, and appears as a separate fuse bit in the JEDEC file. When the power-down feature is not specified in the design file, the IN/PD pin will be configured as a regular logic input. Note: Some programmers list the 22V10 JEDEC compatible 22V10C (no PD used) separately from the non-22V10 JEDEC compatible 22V10CEX (with PD used). 9 0735T-PLD-5/09 10. Compiler Mode Selection Table 10-1. Compiler Mode Selection PAL Mode (5828 Fuses) Synario WINCUPL Note: ATF22V10C (DIP) ATF22V10C (PLCC) P22V10 P22V10LCC GAL Mode (5892 Fuses) ATTF22V10C DIP (UES) ATF22C10C PLCC (UES) G22V10 G22V10LCC Power-down Mode(1) (5893 Fuses) ATF22V10C DIP (PWD) ATF22V10C PLCC (PWD) G22V10CP G22V10CPLCC 1. These device types will create a JEDEC file which when programmed in ATF22V10C devices will enable the power-down mode feature. All other device types have the feature disabled. 10 ATF22V10C(Q) 0735T-PLD-5/09 ATF22V10C(Q) 11. Functional Logic Diagram 11 0735T-PLD-5/09 ATF22V10C/CQ SUPPLY CURRENT VS. SUPPLY VOLTAGE (TA = 25C) 140.0 120.0 100.0 ICC (mA) 80.0 60.0 40.0 20.0 0.0 4.50 4.75 5.00 SUPPLY VOLTAGE (V) 5.25 5.50 C-5, -7, -10 C-15 CQ-15 NORMALIZED ICC 1.0 1.1 ATF22V10C/CQ NORMALIZED ICC VS. TEMPERATURE 0.9 0.8 -40.0 0.0 25.0 75.0 TEMPERATURE (C) ATF22V10C/CQ SUPPLY CURRENT VS. INPUT FREQUENCY (VCC = 5V, TA = 25C) 120.0 C-5, 7, 10 80.0 ICC (mA) C-15 CQ-15 ATF22V10C/CQ OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (V CC = 5V, T A = 25C) 0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 0.0 0.5 1.0 1.5 2.0 2.5 V OH (V) 3.0 3.5 4.0 4.5 5.0 40.0 0.0 0.0 10.0 20.0 50.0 FREQUENCY (MHz) IOH (mA) ATF22V10C/CQ OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (VOH = 2.4V) 0.0 -5.0 -10.0 -15.0 -20.0 -25.0 -30.0 -35.0 -40.0 -45.0 -50.0 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 5.5 6.0 140.0 120.0 100.0 IOL (mA) 80.0 60.0 40.0 20.0 0.0 0.0 ATF22V10C/CQ OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (V OL = 0.5V) IOH (mA) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) ATF22V10C/CQ OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (VOL = 0.5V) 46.0 45.0 44.0 43.0 42.0 41.0 40.0 39.0 38.0 37.0 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 5.5 6.0 0.0 INPUT CURRENT (mA) -20.0 -40.0 -60.0 -80.0 -100.0 -120.0 0.0 ATF22V10C/CQ INPUT CLAMP CURRENT VS. INPUT VOLTAGE (VCC = 5V, TA = 35C) IOL (mA) -0.2 -0.4 -0.6 -0.8 -1.0 INPUT VOLTAGE (V) 12 ATF22V10C(Q) 0735T-PLD-5/09 ATF22V10C(Q) ATF22V10C/CQ NORMALIZED TPD VS. VCC 1.2 NORMALIZED TPD 1.1 1.0 0.9 0.8 4.50 NORMALIZED TCO 1.1 ATF22V10C/CQ NORMALIZED TCO VS. TEMPERATURE 1.0 0.9 4.75 5.00 SUPPLY VOLTAGE (V) 5.25 5.50 0.8 -40.0 0.0 25.0 75.0 TEMPERATURE (C) ATF22V10C/CQ NORMALIZED TCO VS. VCC 1.3 NORMALIZED TCO 1.2 1.1 1.0 0.9 0.8 4.50 NORMALIZED TSU 1.1 ATF22V10C/CQ NORMALIZED T SU VS. TEMPERATURE 1.0 0.9 4.75 5.00 SUPPLY VOLTAGE (V) 5.25 5.50 0.8 -40.0 0.0 25.0 75.0 TEMPERATURE (C) ATF22V10C/CQ NORMALIZED TSU VS. VCC 1.2 NORMALIZED TSU 1.1 1.0 0.9 0.8 4.50 ATF22V10C/CQ DELTA TPD VS. OUTPUT LOADING 8.0 DELTA TPD (ns) 6.0 4.0 2.0 0.0 -2.0 4.75 5.00 SUPPLY VOLTAGE (V) 5.25 5.50 0 50 100 150 200 250 300 OUTPUT LOADING (pF) 1.1 NORMALIZED TPD ATF22V10C/CQ NORMALIZED TPD VS. TEMPERATURE DELTA TPD (ns) ATF22V10C/CQ DELTA TPD VS. NUMBER OF OUTPUT SWITCHING 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 1.0 0.9 0.8 -40.0 0.0 25.0 75.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 TEMPERATURE (C) NUMBER OF OUTPUTS SWITCHING 13 0735T-PLD-5/09 ATF22V10C/CQ DELTA TCO VS. OUTPUT LOADING 8.0 7.0 DELTA TCO (ns) 6.0 5.0 4.0 3.0 2.0 1.0 0.0 50 100 150 200 250 300 NUMBER OF OUTPUTS LOADING DELTA TCO (ns) 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 1.0 2.0 ATF22V10C/CQ DELTA TCO VS. NUMBER OF SWITCHING 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 NUMBER OF OUTPUTS SWITCHING 14 ATF22V10C(Q) 0735T-PLD-5/09 ATF22V10C(Q) 12. Ordering Information 12.1 ATF22V10C(Q) Green Package Options (Pb/Halide-free/RoHS Compliant) tS (ns) 3 3.5 3.5 tCO (ns) 4 4.5 4.5 Ordering Code ATF22V10C-5JX ATF22V10C-7PX ATF22V10C-7SX ATF22V10C-7JU ATF22V10C-10JU ATF22V10C-10PU ATF22V10C-10SU ATF22V10C-10XU ATF22V10C-15JU ATF22V10C-15PU 15 10 8 ATF22V10CQ-15JU 28J Industrial (-40C to 85C) Package 28J 24P3 24S 28J 28J 24P3 24S 24X 28J 24P3 Operation Range Commercial (0C to 70C) Commercial (0C to 70C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) tPD (ns) 5 7.5 7.5 10 4.5 6.5 12.2 Using "C" Product for Industrial To use commercial product for industrial temperature ranges, down-grade one speed grade from the industrial-grade to the commercial-grade device (e.g. 7 ns PX = 10 ns PU) and de-rate power by 30%. 12.3 Military Package Options (Lead-based) tS (ns) tCO (ns) Ordering Code ATF22V10C-10GM/883 ATF22V10C-10NM/883 5962-8984116LA 5962-89841163A ATF22V10C-15GM/883 ATF22V10C-15NM/883 5962-8984115LA 5962-89841153A Package 24D3 28L 24D3 28L 24D3 28L 24D3 28L Operation Range Military (-55C to 125C) Class B, Fully Compliant Military (-55C to 125C) Class B, Fully Compliant tPD (ns) 10 4.5 6.5 15 10 8 Package Type 24D3 24P3 24S 24X 28J 28L 24-lead, 0.300" Wide, Non-windowed Ceramic Dual Inline Package (CERDIP) 24-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP) 24-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 24-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP) 28-lead, Plastic J-leaded Chip Carrier (PLCC) 28-lead, Ceramic Leadless Chip Carrier (LCC) 15 0735T-PLD-5/09 13. Packaging Information 13.1 24D3 - CERDIP Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 D-9 Config A (Glass Sealed) 32.51(1.280) 31.50(1.240) PIN 1 7.87(0.310) 7.24(0.285) 27.94(1.100) REF 5.08(0.200) MAX SEATING PLANE 5.08(0.200) 3.18(0.125) 2.45(0.100)BSC 1.65(0.065) 1.14(0.045) 8.13(0.320) 7.37(0.290) 0.127(0.005) MIN 1.52(0.060) 0.38(0.015) 0.66(0.026) 0.36(0.014) 0.46(0.018) 0.20(0.008) 0~ 15 REF 10.20(0.400) MAX 10/21/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 24D3, 24-lead, 0.300" Wide. Non-windowed, Ceramic Dual Inline Package (Cerdip) DRAWING NO. 24D3 REV. B R 16 ATF22V10C(Q) 0735T-PLD-5/09 ATF22V10C(Q) 13.2 24P3 - PDIP D PIN 1 E1 A SEATING PLANE L B1 e E B A1 C eC eB SYMBOL A A1 D E E1 B Notes: 1. 2. This package conforms to JEDEC reference MS-001, Variation AF. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). B1 L C eB eC e COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.381 31.623 7.620 6.096 0.356 1.270 2.921 0.203 - 0.000 NOM - - - - - - - - - - - MAX 5.334 - 32.131 8.255 7.112 0.559 1.651 3.810 0.356 10.922 1.524 Note 2 Note 2 NOTE 2.540 TYP 6/1/04 2325 Orchard Parkway San Jose, CA 95131 TITLE 24P3, 24-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 24P3 REV. D R 17 0735T-PLD-5/09 13.3 24S - SOIC B D1 PIN 1 ID PIN 1 D e E A COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN - 0.10 10.00 7.40 15.20 0.33 0.40 0.23 NOM - - - - - - - - 1.27 BSC MAX 2.65 0.30 10.65 7.60 15.60 0.51 1.27 0.32 NOTE A1 A A1 D D1 0 ~ 8 L1 E B L L L1 e 06/17/2002 2325 Orchard Parkway San Jose, CA 95131 TITLE 24S, 24-lead (0.300" body) Plastic Gull Wing Small Outline (SOIC) DRAWING NO. 24S REV. B R 18 ATF22V10C(Q) 0735T-PLD-5/09 ATF22V10C(Q) 13.4 24X - TSSOP Dimensions in Millimeter and (Inches)* JEDEC STANDARD MO-153 AD Controlling dimension: millimeters 0.30(0.012) 0.19(0.007) 4.48(0.176) 4.30(0.169) 6.50(0.256) 6.25(0.246) PIN 1 0.65(0.0256)BSC 7.90(0.311) 7.70(0.303) 1.20(0.047)MAX 0.15(0.006) 0.05(0.002) 0 ~ 8 0.20(0.008) 0.09(0.004) 0.75(0.030) 0.45(0.018) 04/11/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 24X, 24-lead (4.4 mm body width) Plastic Thin Shrink Small Outline Package (TSSOP) DRAWING NO. 24X REV. A R 19 0735T-PLD-5/09 13.5 28J - PLCC 1.14(0.045) X 45 PIN NO. 1 IDENTIFIER 1.14(0.045) X 45 0.318(0.0125) 0.191(0.0075) E1 B E B1 D2/E2 e D1 D A A2 A1 0.51(0.020)MAX 45 MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E1 D2/E2 B B1 e MIN 4.191 2.286 0.508 12.319 11.430 12.319 11.430 9.906 0.660 0.330 NOM - - - - - - - - - - 1.270 TYP MAX 4.572 3.048 - 12.573 11.582 12.573 11.582 10.922 0.813 0.533 Note 2 Note 2 NOTE 10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 28J REV. B R 20 ATF22V10C(Q) 0735T-PLD-5/09 ATF22V10C(Q) 13.6 28L - LCC Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 C-4 11.68(0.460) 11.23(0.442) 2.54(0.100) 2.16(0.085) 11.68(0.460) 11.23(0.442) PIN 1 1.40(0.055) 1.14(0.045) 1.91(0.075) 1.40(0.055) 2.41(0.095) 1.91(0.075) INDEX CORNER 0.635(0.025) X 45 0.381(0.015) 0.305(0.012) RADIUS 0.178(0.007) 7.62(0.300) BSC 0.737(0.029) 0.533(0.021) 1.27(0.050) TYP 1.02(0.040) X 45 2.16(0.085) 1.65(0.065) 7.62(0.300) BSC 10/21/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 28L, 28-pad, Non-windowed, Ceramic Lid, Leadless Chip Carrier (LCC) DRAWING NO. 28L REV. B R 21 0735T-PLD-5/09 14. Revision History Revision Level - Revision Date R - June 2006 S - August 2008 T - May 2009 History Updated Green package options. Added new green part. Added military-grade packages and removed leaded parts. 22 ATF22V10C(Q) 0735T-PLD-5/09 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support PLD@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) 2009 Atmel Corporation. All rights reserved. Atmel(R), logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 0735T-PLD-5/09 |
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